1. Field of the Invention
This invention relates to the field of integrated circuit chip design, and in particular to the design of application specific integrated circuits with on-chip memories.
2. Description of the Related Art
It is becoming commonplace to have integrated circuits on a monolithic chip which includes both logic circuitry and memory circuitry. One example of this would be a microprocessor with an on-chip instruction cache. The distinction between the two circuitry types is important in that logic circuitry tolerates and generates a significant amount of electronic noise, whereas high-density memory circuitry must be isolated from sources of electronic noise.
High density memories such as dynamic random access memory (DRAM) store information in the form of charges on a storage capacitor. The stored charge is very tiny (in the pico-farad range), and is detected by the change in voltage it induces on a bit line when the bit line is coupled to the storage capacitor. Electronic noise also induces changes in voltage on the bit line, and these changes may interfere with the detection of the stored charge, which will lead to errors when reading information from the memory.
Several approaches are used to minimize the effects of electronic noise. These include: distancing the memory circuitry from the logic circuitry, placing the memory in an isolation well, and forming a differential signal using two bit lines. In this last approach, a second complementary bit line B' is routed along side the first bit line B, and the voltage change detection is done between the two bit lines. Electronic noise is assumed to couple equally to both bit lines, and hence is canceled by measuring the voltage difference.
In the drive for increasing circuit densities, space is at a premium. The reduction of the actual physical area of the circuit places the logic circuitry in closer proximity to the memory circuitry, and the increased number of devices on the chip implies an increase in the number of electrical connections between devices. The routing of the electrical connections becomes more complex and consumes a greater amount of "routing space". To a large degree, the increased routing space is provided by increasing the number of routing layers, but some expansion can be obtained by increasing the available routing area of each layer.
The space over the memory has heretofore been considered inviolate. Routing logic signals over the memory introduces electronic noise and capacitive coupling in close proximity to the bit lines. Since the source of the electronic noise and capacitive coupling is no longer "far away", the induced voltage changes on bit lines B and B' are no longer the same, and hence no longer cancel out.
It is therefore desirable to provide a system and method which permits the routing of logic signals over an on-chip memory without interfering in the operation of the memory's read operations.